TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
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4.3 Enhanced PWM Modules
The 2833x/2823x devices contain up to six enhanced PWM (ePWM) modules (ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6). Figure 4-4 shows the time-base counter synchronization scheme 3. Figure 4-
5 shows the signal interconnections with the ePWM.
Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register
configuration.
eCAP4
EPWM1SYNCI
GPIO
ePWM1
MUX
EPWM1SYNCO
SYNCI
eCAP1
EPWM4SYNCI
ePWM4
EPWM2SYNCI
ePWM2
EPWM4SYNCO
EPWM2SYNCO
EPWM5SYNCI
ePWM5
EPWM3SYNCI
ePWM3
EPWM5SYNCO
EPWM3SYNCO
EPWM6SYNCI
ePWM6
A. By default, ePWM and HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 4-2 shows this
configuration. To re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of
MAPCNF register (address 0x702E) must be set to 1. Table 4-3 shows the remapped configuration.
Figure 4-4. Time-Base Counter Synchronization Scheme 3
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Peripherals
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