TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
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6-3
Emulator Connection Without Signal Buffering for the DSP ............................................................. 123
6-4
3.3-V Test Load Circuit......................................................................................................... 124
Clock Timing..................................................................................................................... 127
Power-on Reset................................................................................................................. 129
Warm Reset ..................................................................................................................... 130
Example of Effect of Writing Into PLLCR Register ......................................................................... 131
General-Purpose Output Timing .............................................................................................. 132
Sampling Mode ................................................................................................................. 132
General-Purpose Input Timing ................................................................................................ 133
IDLE Entry and Exit Timing.................................................................................................... 134
STANDBY Entry and Exit Timing Diagram .................................................................................. 136
HALT Wake-Up Using GPIOn................................................................................................. 138
PWM Hi-Z Characteristics ..................................................................................................... 139
ADCSOCAO or ADCSOCBO Timing ........................................................................................ 142
External Interrupt Timing....................................................................................................... 142
SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 145
SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 147
SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 149
SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 150
Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 154
Example Read Access ......................................................................................................... 157
Example Write Access ......................................................................................................... 159
Example Read With Synchronous XREADY Access ...................................................................... 161
Example Read With Asynchronous XREADY Access ..................................................................... 162
Write With Synchronous XREADY Access.................................................................................. 164
Write With Asynchronous XREADY Access ................................................................................ 165
External Interface Hold Waveform............................................................................................ 167
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 168
ADC Power-Up Control Bit Timing ........................................................................................... 170
ADC Analog Input Impedance Model ........................................................................................ 171
Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 172
Simultaneous Sampling Mode Timing ....................................................................................... 173
McBSP Receive Timing........................................................................................................ 177
McBSP Transmit Timing ....................................................................................................... 177
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 178
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 179
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 180
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 181
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6
List of Figures
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