SPRS439M – JUNE 2007 – REVISED AUGUST 2012
The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations).
shows the
GPIO register mapping.
Table 4-15. GPIO Registers
NAME
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
GPAPUD
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
GPBPUD
Reserved
GPCMUX1
GPCMUX2
GPCDIR
GPCPUD
Reserved
GPADAT
GPASET
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPBCLEAR
GPBTOGGLE
GPCDAT
GPCSET
GPCCLEAR
GPCTOGGLE
Reserved
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
GPIOXINT3SEL
GPIOXINT4SEL
GPIOXINT5SEL
ADDRESS
0x6F80
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
0x6F8E – 0x6F8F
0x6F90
0x6F92
0x6F94
0x6F96
0x6F98
0x6F9A
0x6F9C
0x6F9E – 0x6FA5
0x6FA6
0x6FA8
0x6FAA
0x6FAC
0x6FAE – 0x6FBF
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
0x6FD0
0x6FD2
0x6FD4
0x6FD6
0x6FD8 – 0x6FDF
0x6FE0
0x6FE1
0x6FE2
0x6FE3
0x6FE4
0x6FE5
SIZE (x16)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
18
2
2
2
2
2
2
2
2
2
2
2
2
8
1
1
1
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO32 to 63)
XINT4 GPIO Input Select Register (GPIO32 to 63)
XINT5 GPIO Input Select Register (GPIO32 to 63)
GPIO A Data Register (GPIO0 to 31)
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 63)
GPIO B Data Set Register (GPIO32 to 63)
GPIO B Data Clear Register (GPIO32 to 63)
GPIOB Data Toggle Register (GPIO32 to 63)
GPIO C Data Register (GPIO64 to 87)
GPIO C Data Set Register (GPIO64 to 87)
GPIO C Data Clear Register (GPIO64 to 87)
GPIO C Data Toggle Register (GPIO64 to 87)
GPIO C MUX1 Register (GPIO64 to 79)
GPIO C MUX2 Register (GPIO80 to 87)
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pull Up Disable Register (GPIO64 to 87)
GPIO B Control Register (GPIO32 to 63)
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPIO B MUX 1 Register (GPIO32 to 47)
GPIO B MUX 2 Register (GPIO48 to 63)
GPIO B Direction Register (GPIO32 to 63)
GPIO B Pull Up Disable Register (GPIO32 to 63)
DESCRIPTION
GPIO A Control Register (GPIO0 to 31)
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
Copyright © 2007–2012, Texas Instruments Incorporated
Peripherals
101
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
