TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
WS (Async)
(A) (B)
(C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
(D)
XWE0, XWE1
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[31:0], XD[15:0]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(D)
(E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes
alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-28. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 1
3
≥ 1
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
6.10.8 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
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Electrical Specifications
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