TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S–APRIL 2001–REVISED MARCH 2011
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Table 4-7. McBSP Registers (continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers(2)
McBSP Data Receive Register 2 – Top of receive FIFO
Read First FIFO pointers will not advance
McBSP Data Receive Register 1 – Top of receive FIFO
Read Second for FIFO pointers to advance
McBSP Data Transmit Register 2 – Top of transmit FIFO
Write First FIFO pointers will not advance
McBSP Data Transmit Register 1 – Top of transmit FIFO
Write Second for FIFO pointers to advance
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
•
•
W
W
•
•
FIFO Control Registers
MFFTX
MFFRX
MFFCT
MFFINT
MFFST
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
0xA000
0x201F
0x0000
0x0000
0x0000
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
(2) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
76
Peripherals
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