SPRS174S – APRIL 2001 – REVISED MARCH 2011
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6.27 External Interface Ready-on-Write Timing With One External Wait State
Table 6-39. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
d(XWEL-XD)
t
h(XA)XZCSH
t
h(XD)XWE
t
dis(XD)XRNW
(1)
(2)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high or low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active-low
Hold time, address valid after zone chip-select inactive-high
Hold time, write data valid after XWE inactive-high
Maximum time for DSP to release the data bus after XR/W inactive-high
(1)
MIN
–2
MAX
1
3
2
2
2
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0
1
4
TW – 2
(2)
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access. See
Table 6-40. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
(1)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip-select high
15
0
15
12
3
MAX
UNIT
ns
ns
ns
ns
ns
The first XREADY (synchronous) sample occurs with respect to E in
E = (XWRLEAD + XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) t
c(XTIM)
– t
su(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Table 6-41. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
t
h(XRDYasynchH)XZCSH
(1)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip-select high
11
0
11
8
3
MAX
UNIT
ns
ns
ns
ns
ns
The first XREADY (synchronous) sample occurs with respect to E in
E = (XWRLEAD + XWRACTIVE – 2) t
c(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) t
c(XTIM)
– t
su(XRDYasynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
136
Electrical Specifications
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