SPRS174S – APRIL 2001 – REVISED MARCH 2011
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6.29 XHOLD/XHOLDA Timing
Table 6-42. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
(1) (2)
MIN
t
d(HL-HiZ)
t
d(HL-HAL)
t
d(HH-HAH)
t
d(HH-BV)
(1)
(2)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
MAX
4t
c(XTIM)
5t
c(XTIM)
3t
c(XTIM)
4t
c(XTIM)
UNIT
ns
ns
ns
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
High-Impedance
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
Valid
High-Impedance
Valid
XD[15:0]
Valid
See Note (A)
See Note (B)
A.
B.
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-37. External Interface Hold Waveform
140
Electrical Specifications
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