欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320F2812PGFS 参数 Datasheet PDF下载

TMS320F2812PGFS图片预览
型号: TMS320F2812PGFS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 170 页 / 1662 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320F2812PGFS的Datasheet PDF文件第106页浏览型号TMS320F2812PGFS的Datasheet PDF文件第107页浏览型号TMS320F2812PGFS的Datasheet PDF文件第108页浏览型号TMS320F2812PGFS的Datasheet PDF文件第109页浏览型号TMS320F2812PGFS的Datasheet PDF文件第111页浏览型号TMS320F2812PGFS的Datasheet PDF文件第112页浏览型号TMS320F2812PGFS的Datasheet PDF文件第113页浏览型号TMS320F2812PGFS的Datasheet PDF文件第114页  
SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
Table 6-16. HALT Mode Timing Requirements
MIN
t
w(WAKE-XNMI)
t
w(WAKE-XRS)
Pulse duration, XNMI wakeup signal
Pulse duration, XRS wakeup signal
2t
c(CI)
8t
c(CI)
NOM
MAX
UNIT
cycles
cycles
Table 6-17. HALT Mode Switching Characteristics
PARAMETER
t
d(IDLE-XCOH)
t
p
Delay time, IDLE instruction executed to XCLKOUT high
PLL lock-up time
Delay time, PLL lock to program execution resume
t
d(WAKE)
Wake up from flash
– Flash module in sleep state
Wake up from SARAM
1125t
c(SCO)
35t
c(SCO)
cycles
cycles
MIN
32t
c(SCO)
TYP
45t
c(SCO)
131072t
c(CI)
MAX
UNIT
cycles
cycles
A
B
Device
Status
Flushing Pipeline
C
D
HALT
HALT
PLL Lock-up Time
Wake-up Latency
E
F
G
Normal
Execution
XNMI
t
w(WAKE-XNMI)
t
p
t
d(wake)
X1/XCLKIN
t
d(IDLE-XCOH)
XCLKOUT
(H)
Oscillator Start-up Time
32 SYSCLKOUT Cycles
A.
B.
C.
D.
E.
F.
G.
H.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT
mode and consumes absolute minimum power.
When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2t
c(CI)
is
applicable when an external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be
added to this parameter.
When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
Normal operation resumes.
XCLKOUT = SYSCLKOUT
Figure 6-17. HALT Wakeup Using XNMI
110
Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
Product Folder Link(s):