TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
表9-30. GPIOA MUX
DEFAULT AT RESET
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
PRIMARY I/O
FUNCTION(1) (2)
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00)
(GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
1-0
GPIO0
GPIO1
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
Reserved
Reserved
Reserved
Reserved
COMP1OUT (O)
Reserved
3-2
5-4
GPIO2
Reserved
7-6
GPIO3
Reserved
COMP2OUT(3) (O)
9-8
GPIO4
Reserved
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO5
Reserved
ECAP1 (I/O)
EPWMSYNCO (O)
Reserved
GPIO6
EPWMSYNCI (I)
SCIRXDA (I)
Reserved
GPIO7
Reserved
Reserved
Reserved
Reserved
GPIO12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ1 (I)
SCITXDA (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00)
(GPAMUX2 BITS = 01)
(GPAMUX2 BITS = 10)
(GPAMUX2 BITS = 11)
1-0
GPIO16
GPIO17
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
Reserved
Reserved
Reserved
SCITXDA (O)
SCIRXDA (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDAA (I/OD)
SCLA (I/OD)
Reserved
Reserved
TZ2 (I)
TZ3 (I)
3-2
5-4
GPIO18
XCLKOUT (O)
ECAP1 (I/O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ2 (I)
7-6
GPIO19/XCLKIN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO28
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCIRXDA (I)
SCITXDA (O)
Reserved
GPIO29
TZ3 (I)
Reserved
Reserved
Reserved
Reserved
Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These functions are not available in the 38-pin package.
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