TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.18 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17
Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
RW,+00001
TOUTPSEL0
RW,+00000
R,+000000000000000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-19
Timer Output Selection Field Description (TOUTPSEL)
Bit
Field
Description
31-10
9-5
Reserved
Reserved
TOUTPSEL1
Output select for TIMO1
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000: TOUTL4
01001: TOUTH4
01010: TOUTL5
01011: TOUTH5
01100: TOUTL6
01101: TOUTH6
01110: TOUTL7
01111: TOUTH7
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
4-0
TOUTPSEL0
Output select for TIMO0
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000: TOUTL4
01001: TOUTH4
01010: TOUTL5
01011: TOUTH5
01100: TOUTL6
01101: TOUTH6
01110: TOUTL7
01111: TOUTH7
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
End of Table 3-19
94
Device Configuration
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