TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.4.3 Soft Reset
A soft reset will behave like a hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs and the PCIe MMRs sticky
bits, and external memory contents are retained. POR should also remain de-asserted during this time.
Soft reset is initiated by the following
•
•
•
RESET pin
RSCTRL register in PLLCTL
Watchdog timer
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers
are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in
self-refresh mode before invoking the soft reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
controllers pause their system clocks for about 8 cycles.
At this point:
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›
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The state of the peripherals before the soft reset is not changed.
The I/O pins are controlled as dictated by the DEVSTAT register.
The DDR3 MMRs and the PCIe MMRs sticky bits retain their previous values. Only the DDR3
Memory Controller and PCIe state machines are reset by the soft reset.
›
The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with
a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 135
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