TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following
•
•
•
•
RESET pin
RSCTRL register in PLLCTL
Watchdog timer
Emulation
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a hard reset:
1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is
able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
together with the POR pin.
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Peripheral Information and Electrical Specifications
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