TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
The following figure shows the connection between masters and slaves on TeraNet 3P and TeraNet 6P.
Figure 4-3
TeraNet 3P_A & B for C6678
MPU (× 4)
S
S
S
Bridge_12
TC (× 2)
From TeraNet_3_A
TNet_2P
CPU/2
Bridge_13
Bridge_14
CC0
TC (× 4)
S
S
TNet_3P_C
CPU/3
CC1
CorePac_n*
M
TC (× 4)
S
S
TNet_3P_D
CPU/3
CC2
MPU_2
MPU_3
QM_SS
S
S
Tracer_QM_CFG
Tracer_SM
Semaphore
TETB (Debug_SS)
TETB (for core)
To TeraNet_3P_Tracer
MPU_0
Tracer_CFG
SRIO
S
Tracer
S
NETCP
S
TSIP0
S
TSIP1
S
To TeraNet_6P_B
Bridge_20
* n varies with the number of CorePacs present in the specific device.
102
System Interconnect
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