TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 4-2
TeraNet 3A for C6678
Bridge_1
Bridge_2
Bridge_3
Bridge_4
From TeraNet_2_A
CorePac_n*
S
S
S
S
S
S
S
Tracer_L2_n*
PCIe
SRIO_M
M
M
MPU_1
QM_SS
PCIe
Tracer_QM_M
SRIO
Packet DMA
M
M
M
SRIO
SPI
NETCP
TNet_6P_A
CPU/3
Boot_ROM
QM_SS
Packet DMA
EMIF16
QM_SS
Second
M
TNet_3_D
CPU/3
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
Debug_SS
TSIP0
M
M
M
TNet_3_C
CPU/3
To TeraNet_2_A
TSIP1
TC_0
TC_1
M
M
M
M
EDMA
CC1
TC_2
TC_3
Bridge_12
Bridge_13
Bridge_14
TC_0
TC_1
TC_2
TC_3
M
M
M
M
To TeraNet_3P_A
EDMA
CC2
* n varies with the number of CorePacs present in the specific device.
100
System Interconnect
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