TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Allowed connections on TeraNet 3P and TeraNet 6P are summarized in the following tables.
Intersecting cells may contain one of the following:
•
•
•
Y — There is a direct connection between this master and that slave.
- — There is NO connection between this master and that slave.
n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 4-2
Configuration Switch Fabric Connection Matrix Section1 (Part 1 of 2)
Slave
Masters
HyperLink_Master
EDMA3CC0_TC0_RD
EDMA3CC0_TC0_WR
EDMA3CC0_TC1_RD
EDMA3CC0_TC1_WR
EDMA3CC1_TC0_RD
EDMA3CC1_TC0_WR
EDMA3CC1_TC1_RD
EDMA3CC1_TC1_WR
EDMA3CC1_TC2_RD
EDMA3CC1_TC2_WR
EDMA3CC1_TC3_RD
EDMA3CC1_TC3_WR
EDMA3CC2_TC0_RD
EDMA3CC2_TC0_WR
EDMA3CC2_TC1_RD
EDMA3CC2_TC1_WR
EDMA3CC2_TC2_RD
EDMA3CC2_TC2_WR
EDMA3CC2_TC3_RD
EDMA3CC2_TC3_WR
SRIO packet DMA
SRIO_Master
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12 1,12 1,12 1,12
1,12
1,12
1,12 1,12 1,12 1,12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
PCIe_Master
NETCP packet DMA
MSMC_Data_Master
QM packet DMA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
QM_Second
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DebugSS_Master
TSIP0_Master
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
TSIP1_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC0
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
Copyright 2012 Texas Instruments Incorporated
System Interconnect 97
TI [ TEXAS INSTRUMENTS ]
