TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
5 C66x CorePac
The C66x CorePac consists of several components:
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The C66x DSP and associated C66x CorePac core
Level-one and level-two memories (L1P, L1D, L2)
Data Trace Formatter (DTF)
Embedded Trace Buffer (ETB)
Interrupt Controller
Power-down controller
External Memory Controller
Extended Memory Controller
A dedicated power/sleep controller (LPSC)
The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the
C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.
Figure 5-1
C66x CorePac Block Diagram
32KB L1P
Program Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
L2 Cache/
SRAM
512KB
C66x DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
MSM
SRAM
4096KB
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path A
Data Path B
DDR3
SRAM
A Register File
B Register File
PLLC
LPSC
GPSC
A31-A16
A15-A0
B31-B16
B15-B0
DMA Switch
Fabric
.M1
.L1 .S1 xx .D1
xx
.M2
.D2 xx .S2 .L2
xx
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
CFG Switch
Fabric
32KB L1D
For more detailed information on the TMS320C66x CorePac on the C6672 device, see the C66x CorePac User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 69.
Copyright 2012 Texas Instruments Incorporated
C66x CorePac 101
TI [ TEXAS INSTRUMENTS ]
