TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 2-2
Memory Map Summary (Part 5 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
60K
Description
02801000
02810000
02811000
02820000
02821000
02830000
02831000
02840000
02841000
02850000
02858000
02860000
02900000
02921000
02A00000
02C00000
08000000
08010000
0BC00000
0BD00000
0C000000
0C400000
10800000
10880000
10900000
10E00000
10E08000
10F00000
10F08000
11800000
11880000
11900000
11E00000
11E08000
11F00000
11F08000
12800000
12880000
12900000
12E00000
12E08000
12F00000
12F08000
0280FFFF
02810FFF
0281FFFF
02820FFF
0282FFFF
02830FFF
0283FFFF
02840FFF
0284FFFF
02857FFF
0285FFFF
028FFFFF
02920FFF
029FFFFF
02BFFFFF
07FFFFFF
0800FFFF
0BBFFFFF
0BCFFFFF
0BFFFFFF
0C3FFFFF
107FFFFF
1087FFFF
108FFFFF
10DFFFFF
10E07FFF
10EFFFFF
10F07FFF
117FFFFF
1187FFFF
118FFFFF
11DFFFFF
11E07FFF
11EFFFFF
11F07FFF
127FFFFF
1287FFFF
128FFFFF
12DFFFFF
12E07FFF
12EFFFFF
12F07FFF
137FFFFF
0 02801000
0 02810000
0 02811000
0 02820000
0 02821000
0 02830000
0 02831000
0 02840000
0 02841000
0 02850000
0 02858000
0 02860000
0 02900000
0 02921000
0 02A00000
0 02C00000
0 08000000
0 08010000
0 0BC00000
0 0BD00000
0 0C000000
0 0C400000
0 10800000
0 10880000
0 10900000
0 10E00000
0 10E08000
0 10F00000
0 10F08000
0 11800000
0 11880000
0 11900000
0 11E00000
0 11E08000
0 11F00000
0 11F08000
0 12800000
0 12880000
0 12900000
0 12E00000
0 12E08000
0 12F00000
0 12F08000
0 0280FFFF
0 02810FFF
0 0281FFFF
0 02820FFF
0 0282FFFF
0 02830FFF
0 0283FFFF
0 02840FFF
0 0284FFFF
0 02857FFF
0 0285FFFF
0 028FFFFF
0 02920FFF
0 029FFFFF
0 02BFFFFF
0 07FFFFFF
0 0800FFFF
0 0BBFFFFF
0 0BCFFFFF
0 0BFFFFFF
0 0C3FFFFF
0 107FFFFF
0 1087FFFF
0 108FFFFF
0 10DFFFFF
0 10E07FFF
0 10EFFFFF
0 10F07FFF
0 117FFFFF
0 1187FFFF
0 118FFFFF
0 11DFFFFF
0 11E07FFF
0 11EFFFFF
0 11F07FFF
0 127FFFFF
0 1287FFFF
0 128FFFFF
0 12DFFFFF
0 12E07FFF
0 12EFFFFF
0 12F07FFF
0 137FFFFF
Reserved
4K
Reserved
60K
Reserved
4K
Reserved
60K
Reserved
4K
Reserved
60K
Reserved
4K
Reserved
60K
Reserved
32K
TI embedded trace buffer (TETB) — system
32K
Reserved
640K
132K
1M-132K
2M
Reserved
Serial RapidIO (SRIO) configuration
Reserved
Queue manager subsystem configuration
84M
64K
Reserved
Extended memory controller (XMC) configuration
60M-64K
1M
Reserved
Multicore shared memory controller (MSMC) config
3M
Reserved
4M
Multicore shared memory (MSM)
Reserved
68 M
512K
512K
5M
CorePac0 L2 SRAM
Reserved
Reserved
32K
CorePac0 L1P SRAM
Reserved
1M-32K
32K
CorePac0 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac1 L2 SRAM
Reserved
Reserved
32K
CorePac1 L1P SRAM
Reserved
1M-32K
32K
CorePac1 L1D SRAM
Reserved
9M-32K
512K
512K
5M
Reserved
Reserved
Reserved
32K
Reserved
1M-32K
32K
Reserved
Reserved
9M-32K
Reserved
Copyright 2012 Texas Instruments Incorporated
Device Overview 25
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