TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
5.1.2 L1D Memory
The L1D memory configuration for the C6672 device is as follows:
32K bytes with no wait states
•
Figure 5-3 shows the available SRAM/cache configurations for L1D.
Figure 5-3
L1D Memory Configurations
L1D mode bits
010
Block base
address
00F0 0000h
000
001
011
100
L1D memory
16K bytes
1/2
SRAM
3/4
SRAM
7/8
SRAM
All
SRAM
2-way
cache
00F0 4000h
00F0 6000h
8K bytes
2-way
cache
4K bytes
4K bytes
2-way
cache
00F0 7000h
00F0 8000h
2-way
cache
Copyright 2012 Texas Instruments Incorporated
C66x CorePac 103