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TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ  
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ  
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)  
Write  
Latency =  
1
ECLKOUTx  
1
1
3
CEx  
2
ABE[7:0] or BBE[1:0]  
BE1  
BE2  
EA2  
BE3  
EA3  
Q2  
BE4  
EA4  
Q3  
5
4
AEA[22:3] or BEA[20:1]  
AED[63:0] or BED[15:0]  
EA1  
10  
10  
11  
8
Q1  
Q4  
8
ARE/SDCAS/SADS/SRE  
AOE/SDRAS/SOE  
12  
12  
AWE/SDWE/SWE  
These C64xdevices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a  
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable  
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for  
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].  
§
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space  
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.  
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):  
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency  
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency  
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued  
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).  
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles  
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).  
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2  
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during  
programmable synchronous interface accesses.  
Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB  
†‡§  
(With Write Latency = 1)  
93  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
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