ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING
†
timing requirements for programmable synchronous interface cycles for EMIFA module
(see Figure 24)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
6
7
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
2
ns
ns
su(EDV-EKOxH)
1.5
h(EKOxH-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
switching characteristics over recommended operating conditions for programmable
†‡
synchronous interface cycles for EMIFA module (see Figure 24−Figure 26)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
4.9
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SADS/SRE valid
Delay time, ECLKOUTx high to, SOE valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SWE valid
1.3
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
4.9
3
4
4.9
5
1.3
1.3
1.3
8
4.9
4.9
4.9
9
10
11
12
1.3
1.3
4.9
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
89
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