ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
SYNCHRONOUS DRAM TIMING
†
timing requirements for synchronous DRAM cycles for EMIFA module (see Figure 27)
−600
−720
−850
−1G
NO.
UNIT
MIN MAX
6
7
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
0.6
1.8
2.0
ns
ns
ns
su(EDV-EKO1H)
CV
CV
= 1.2 V
= 1.1 V
DD
DD
h(EKO1H-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles
†
for EMIFA module (see Figure 27−Figure 34)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
4.9
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SDCAS valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SDWE valid
Delay time, ECLKOUTx high to SDRAS valid
Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
Delay time, ECLKOUTx high to PDT valid
1.3
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-ACKEV)
d(EKO1H-PDTV)
4.9
3
4
4.9
5
1.3
1.3
8
4.9
4.9
9
10
11
12
13
14
1.3
1.3
1.3
1.3
1.3
4.9
4.9
4.9
4.9
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
