ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
peripheral register descriptions (continued)
Table 7. EDMA Registers
HEX ADDRESS RANGE
01A0 FF9C
01A0 FFA4
ACRONYM
EPRH
CIPRH
CIERH
CCERH
ERH
REGISTER NAME
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
Event enable high register
01A0 FFB8
Event clear high register
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
Event set high register
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
PQSR
CIPRL
CIERL
CCERL
ERL
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
EERL
Event enable low register
01A0 FFF8
ECRL
ESRL
Event clear low register
01A0 FFFC
01A1 0000 − 01A3 FFFF
Event set low register
–
Reserved
19
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