ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
for EMIFA and EMIFB modules (see Figure 36)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
5.5
1
2
t
t
Delay time, AECLKOUTx high to ABUSREQ valid
Delay time, BECLKOUTx high to BBUSREQ valid
1
ns
ns
d(AEKO1H-ABUSRV)
0.9
5.5
d(BEKO1H-BBUSRV)
ECLKOUTx
1
2
1
2
ABUSREQ
BBUSREQ
Figure 36. BUSREQ Timing for EMIFA and EMIFB
105
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