TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Table 4-12. SPI-C Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7760
0x7761
0x7762
0x7764
0x7766
0x7767
0x7768
0x7769
0x776A
0x776B
0x776C
0x776F
SIZE (X16)
DESCRIPTION(1)
SPI-C Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI-C Operation Control Register
SPI-C Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-C Baud Rate Register
SPI-C Receive Emulation Buffer Register
SPI-C Serial Input Buffer Register
SPI-C Serial Output Buffer Register
SPI-C Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-C FIFO Transmit Register
SPI-C FIFO Receive Register
SPI-C FIFO Control Register
SPI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-13. SPI-D Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
SIZE (X16)
DESCRIPTION(1)
SPI-D Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI-D Operation Control Register
SPI-D Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-D Baud Rate Register
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Peripherals
75
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