TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Figure 4-13 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
TXSHF
SCITXD
TXENA
Register
Parity
TX EMPTY
Even/Odd Enable
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
SCICTL2.0
8
TX FIFO
Interrupts
TXINT
TX FIFO _0
TX Interrupt
Logic
TX FIFO _1
-----
SCITXBUF.7-0
To CPU
TX FIFO _15
SCI TX Interrupt select logic
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
BRKDT
RX FIFO _15
SCIRXST.5
-----
RX FIFO _0
RX FIFO
Interrupts
RX FIFO_1
RXINT
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram
72
Peripherals
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