TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Table 3-4. Addresses of Flash Sectors in F2801/9501, F28015, F28016
ADDRESS RANGE
0x3F 4000 - 0x3F 4FFF
0x3F 5000 - 0x3F 5FFF
0x3F 6000 - 0x3F 6FFF
0x3F 7000 - 0x3F 7F7F
0x3F 7F80 - 0x3F 7FF5
PROGRAM AND DATA SPACE
Sector D (4K x 16)
Sector C (4K x 16)
Sector B (4K x 16)
Sector A (4K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the
code-security passwords are programmed. If security is not a concern, addresses
0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 –
0x3F7FF5 are reserved for data variables and should not contain program code.
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-5.
Table 3-5. Wait-states
AREA
WAIT-STATES COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
0-wait
Fixed
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Fixed. The eCAN peripheral can extend a cycle as needed.
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
L0 & L1 SARAMs
0-wait
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section 3.2.5
for more information.
Programmable,
1-wait minimum
OTP
Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See
Section 3.2.5 for more information.
Flash
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
3.2 Brief Descriptions
32
Functional Overview
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