TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Table 2-3. Signal Descriptions (continued)
PIN NO.
GGM/
ZGM
BALL #
(1)
NAME
DESCRIPTION
PZ
PIN #
VDD
VDD
VDD
VDD
VDD
VDD
10
42
59
68
85
93
3
E2
G6
F10
D7
B6
D4
C2
H7
E9
A7
B1
E3
H6
K9
H10
F7
CPU and Logic Digital Power Pins (1.8 V)
VDDIO
VDDIO
VDDIO
VDDIO
VSS
46
65
82
2
Digital I/O Power Pin (3.3 V)
VSS
11
41
49
55
62
69
77
87
89
94
VSS
VSS
VSS
VSS
Digital Ground Pins
VSS
D10
A9
D6
A5
A4
VSS
VSS
VSS
VSS
GPIOA AND PERIPHERAL SIGNALS(2)(3)
(4)
GPIO0
General purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
General purpose input/output 1 (I/O/Z)(4)
Enhanced PWM1 Output B (O)
SPI-D slave in, master out (I/O) (not available on 2801/9501, 2802)
-
General purpose input/output 2 (I/O/Z)(4)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
General purpose input/output 3 (I/O/Z)(4)
Enhanced PWM2 Output B (O)
SPI-D slave out, master in (I/O) (not available on 2801/9501, 2802)
-
General purpose input/output 4 (I/O/Z)(4)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
General purpose input/output 5 (I/O/Z)(4)
Enhanced PWM3 output B (O)
SPI-D clock (I/O) (not available on 2801/9501, 2802)
Enhanced capture input/output 1 (I/O)
47
44
45
48
51
53
K8
K7
J7
J8
J9
H9
GPIO1
EPWM1B
SPISIMOD
-
GPIO2
EPWM2A
-
-
GPIO3
EPWM2B
SPISOMID
-
GPIO4
EPWM3A
-
-
GPIO5
EPWM3B
SPICLKD
ECAP1
(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
Introduction
21
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