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TLV320AIC23BPWR 参数 Datasheet PDF下载

TLV320AIC23BPWR图片预览
型号: TLV320AIC23BPWR
PDF下载: 下载PDF文件 查看货源
内容描述: 具有集成耳机放大器立体声音频编解码8至96 kHz [STEREO AUDIO CODEC 8 TO 96 KHZ WITH INTEGRATED HEADPHONE AMPLIFIER]
分类和应用: 放大器
文件页数/大小: 50 页 / 490 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TLV320AIC23BPWR的Datasheet PDF文件第25页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第26页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第27页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第28页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第30页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第31页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第32页浏览型号TLV320AIC23BPWR的Datasheet PDF文件第33页  
3.3.2 Audio Sampling Rates  
The TLV320AIC23B can operate in master or slave clock mode. In the master mode, the TLV320AIC23B clock and  
sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB  
specification. The TLV320AIC23B can be used directly in a USB system.  
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control  
the TLV320AIC23B clock and sampling rates.  
The settings in the sample rate control register control the clock mode and sampling rates.  
Sample Rate Control (Address: 0001000)  
BIT  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Function  
X
CLKOUT  
CLKIN  
SR3  
SR2  
SR1  
SR0  
BOSR  
USB/Nor-  
mal  
Default  
0
0
0
1
0
0
0
0
0
CLKOUT  
CLKIN  
Clock output divider  
Clock input divider  
0 = MCLK  
0 = MCLK  
1 = MCLK/2  
1 = MCLK/2  
SR[3:0]  
BOSR  
Sampling rate control (see Sections 3.3.2.1 and 3.3.2.2)  
Base oversampling rate  
USB mode:  
0 = 250 f  
0 = 256 f  
0 = Normal  
1 = 272 f  
1 = 384 f  
1 = USB  
s
s
s
s
Normal mode:  
Clock mode select:  
Reserved  
USB/Normal  
X
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate  
generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN  
to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. The  
following sampling-rate tables are based on CLKIN = MCLK.  
3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)  
In the USB mode, the following ADC and DAC sampling rates are available:  
SAMPLING RATE  
SAMPLING-RATE CONTROL SETTINGS  
FILTER TYPE  
ADC  
(kHz)  
DAC  
(kHz)  
SR3  
SR2  
SR1  
SR0  
BOSR  
96  
88.2  
48  
96  
88.2  
48  
3
2
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
0
1
0
1
44.1  
32  
44.1  
32  
8.021  
8
8.021  
8
48  
8
44.1  
8
8.021  
48  
8.021  
44.1  
The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-kHz, and  
88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figures 3−17 through 3−34 for filter responses  
3−9