TLC5970
SBVS140 –MARCH 2010
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SDTA
SDTB
SCKA
SCKB
Generated Shift Data
(Internal)
D39A D38A D37A D36A D35A
D6A
34
D5A
35
D4A
36
D3A
37
D2A D1A D0A
38 39 40
1
2
3
4
5
Generated Shift Data
(Internal)
Shift Register Bit 0
(Internal)
D35A
D36A
D37A
D0
RD0 D39A D38A D37A D36A
D6A D5A
D7A D6A
D8A D7A
D4A D3A
D5A D4A
D6A D5A
D2A D1A
D3A D2A
D4A D3A
D0A
D1A
D2A
Shift Register Bit 1
(Internal)
D1
RD1
RD2
RD0 D39A D38A D37A
RD1 RD0 D39A D38A
Shift Register Bit 2
(Internal)
D2
RDn are the SID or
EEPROM read data.
Shift Register Bit 38
(Internal)
RD33
RD34
D38
D37
D38
D36 RD35 RD34
RD4 RD3 RD2
RD1 RD0 D39A D38A
Shift Register Bit 39
(Internal)
D39
D37
D36 RD35
RD5 RD4 RD3 RD2
RD1 RD0
D39A
SDTY
SDTZ
D39+ D38+ D37+ D36+ D35+
RD5+ RD4+ RD3+ RD2+ RD1+ RD0+ D39A+
D39- D38- D37- D36- D35-
RD5- RD4- RD3- RD2- RD1- RD0- D39A-
SCKY
SCKZ
Latch Pulse
(Internal)
Addressed Latch Bit 0
(Internal)
D0
D1
D2
Addressed Latch Bit 1
(Internal)
Addressed Latch Bit 2
(Internal)
Addressed Latch Bit 34
(Internal)
D34
D35
Addressed Latch Bit 35
(Internal)
Figure 20. Serial Data Input/Output Timing Diagram 2 (SID/EEPROM Data Read)
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