TLC5970
www.ti.com
SBVS140 –MARCH 2010
SDTA
SDTB
SCKA
SCKB
Generated Shift Data
(Internal)
D39
D38
D37
D36
D35
D6
D5
35
D4
36
D3
37
D2
38
D1
39
D0
40
1
2
3
4
5
34
Generated Shift Data
(Internal)
Shift Register Bit 0
(Internal)
D39
D38
D37
D36 D35
D37 D36
D38 D37
D6
D5
D4
D5
D6
D3
D2
D1
D0
Shift Register Bit 1
(Internal)
D39
D38
D39
D7
D8
D6
D7
D4
D5
D3
D4
D2
D3
D1
D2
Shift Register Bit 2
(Internal)
Shift Register Bit 38
(Internal)
D39 D38
D39
Shift Register Bit 39
(Internal)
SDTY
SDTZ
SCKY
SCKZ
Latch pulse is generated with
the programmed internal latch
delay time from last rising edge
of the shift clock.
Latch Pulse
(Internal)
Addressed Latch Bit 0
(Internal)
D0
Addressed Latch Bit 1
(Internal)
D1
D2
Addressed Latch Bit 2
(Internal)
Addressed Latch Bit 34
(Internal)
D34
D35
Addressed Latch Bit 35
(Internal)
Figure 19. Serial Data Input/Output Timing Diagram 1
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): TLC5970
TI [ TEXAS INSTRUMENTS ]
