TLC5970
SBVS140 –MARCH 2010
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
SDTA
DAP
12
RHP
I/O
DESCRIPTION
6
7
I
I
Noninverting serial data input
Inverting serial data input
SDTB
13
Noninverting data shift clock input. All data in the Common Shift Register are shifted to the
MSB side by 1 bit and synchronized to the rising edge of the differential clock generated by
SCKA and SCKB. The differential data made by SDTA and SDTB are shifted into the
Common Shift Register LSB at the same time.
SCKA
15
16
9
I
I
Inverting data shift clock input. All data in the shift register are shifted to the MSB side by 1 bit
synchronized to the rising edge of the differential clock generated by SCKA and SCKB. The
differential data made by SDTA and SDTB are shifted into the Common Shift Register LSB at
the same time.
SCKB
10
SDTY
SDTZ
SCKY
SCKZ
21
20
18
17
16
15
13
12
O
O
O
O
Noninverting serial data output
Inverting serial data output
Noninverting serial data shift clock output
Inverting serial data shift clock output
Disable buck converter. When SWOFF is connected to VREG, the buck converter is not
operated and the OVP/SCP flag is not set even if the device is in an error condition. When
SWOFF is low, the buck converter is operated. This terminal is internally pulled down to GND
by approximately a 10 kΩ resistor.
SWOFF
2
27
I
EEPROM writing power supply. When this pin level is 19 V, EEPROM can be programmed for
dot correction data. This pin must be open in normal operation. This terminal is pulled down to
GND by approximately a 10 kΩ resistor internally.
VROM
10
5
IREF0
IREF1
IREF2
OUT0
OUT1
OUT2
8
7
4
3
I/O
I/O
I/O
O
The resistors connected from IREF0, IREF1, and IREF2 to GND set the maximum sink current
for OUT0, OUT1, and OUT2, respectively.
6
2
23
24
25
17
18
19
Constant-current sink output. Multiple outputs can be tied together to increase the
constant-current capability.
O
O
Internal regulator output. This pin requires a 0.01 µF decoupling capacitor to ground. This
output cannot be used for any other function and no current can be pulled from this output.
VREG
3
28
O
Internal regulator output for the differential interface circuit. This pin requires a 0.1 µF
decoupling capacitor. This output cannot be used for any other function and no current can be
pulled from this output.
VREGIF
4
1
O
Feedback voltage input for the converter and power-supply for differential signal interface
output and LED driver. Connect this pin to the dc/dc converter output voltage. The FB pin
must not be opened, otherwise higher voltage than the absolute maximum voltage is
generated.
FB
27
20
I
PH
30
29
22
21
O
Source of the high-side power MOSFET. Connected to an external inductor and diode.
Boost capacitor for the high-side power MOSFET gate driver. A capacitor is connected
between BOOT and PH.
BOOT
I/O
VCC
GND
32
1
24
26
—
—
Power-supply voltage
Power ground
5, 9, 11, 14,
19, 22, 26,
28, 31
No internal connection. These pins are not electrically connected to the IC. They should be
soldered to the PCB. Connecting these pins to ground provides improved thermal
performance.
8, 11, 14,
23, 25
NC
The DAP package thermal pad is electrically connected to ground inside the package. This
pad should be connected to the ground plane on the PCB for best thermal performance. It
does not need to be soldered to the PCB if thermal performance is not needed. This pad
cannot be connected to any other voltage other than ground. See the mechanical drawings at
the end of this document for more information.
Thermal
pad
—
—
—
The RHP package thermal pad is electrically connected to ground inside the package. This
pad must be connected to the ground plane on the PCB for best thermal performance and for
mechanical reasons. This pad cannot be connected to any other voltage other than ground.
See the mechanical drawings at the end of this document for more information.
12
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