TLC5970
SBVS140 –MARCH 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
FB
OVP/SCP
FB
VREG
BOOT
PH
Voltage
Reference
Voltage Control
with Soft-Start,
Overvoltage Protection,
Switch
Timing
Control
SWOFF
PH
High-Side
MOS SW
and Short-Circuit Protection
FB
5-V
Regulator
10-MHz
OSC
VREG
OUT 0
OUT 1
1/2
CLK
SEL
Display
Timing
Control
Constant-Current
Control
VREG
UVLO
OUT 2
CLKSEL
DSPRST
AUTORPT
36
7
21
Thermal
Detector
BC Data
MSB
IREF0
IREF1
IREF2
LSB
DC
Data
7-Bit Brightness
Control Second Latch
VROM
3
ROM Write
Control
GS
Data
7
LSB
MSB
12-Bit Function Control
Data Latch
EEPROM
(36-Bit)
0
11
8
29
DC
Loadcnt
13
LSB
MSB
20
VCC
FB
21-Bit Dot Correction
Data Latch
TIMESEL
0
Select
Switch
Latch
Pulse Gen
21
LSB
MSB
36-Bit Grayscale
Second Data Latch
5-V
Regulator
VREGIF
0
35
Address/Command
36
LSB
MSB
36-Bit Grayscale
First Data Latch
Differential
Line Driver
Differential
Line Receiver
19
0
35
SDTA
SDTY
SDTZ
LSB
MSB
39
3
40-Bit Common Shift Register
SDTB
SCKA
0
Clock
Timing
Adjust
SCKY
SCKZ
SCKB
GND
10
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