TLC5945
www.ti.com
SLVS755–MARCH 2007
Figure 14. The next SCLK pulse, which will be the clock for receiving the MSB of the next grayscale data,
transmits MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status
flag becomes active. The LOD status flag is an internal signal which pulls XERR pin down to low when the LOD
status flag becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink
current to the time LOD status flag becomes valid.
MSB
0
LSB
191
15
16
23
X
24
119
120
X
LOD 15
LOD 0
TEF
X
DC 15.5
DC 0.0
X
LOD Data
TEF
DC Values
Reserved
Figure 13. Status Information Data Packet Format
MODE
GS Data Input Mode
XLAT
SIN
1st GS Data Input Cycle
2nd GS Data Input Cycle
GS1
MSB
GS1
LSB
GS2
MSB
GS2
LSB
> t
+ t
pd3
pd2
t
suLOD
1
192
192
193
1
SCLK
SOUT
BLANK
GSCLK
GS1
MSB
SID1
MSB-1
GS2
MSB
SID1
LSB
SID1
MSB
-
-
(1st GS Data Output Cycle)
4096
1
t
pd3
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
t
t
pd2 + pd3
Figure 14. Readout Status Information Data (SID) Timing Chart
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5945 compares the grayscale value of
17
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
