TLC5945
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SLVS755–MARCH 2007
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 15). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.
GS PWM
Cycle n
GS PWM
Cycle n+1
BLANK
GSCLK
t
wl1
t
t
su4
t
wh1
1
t
h4
wh3
4096
2
3
1
t
wl1
t
t
t
pd3
pd1
pd3
OUT0
(Current)
t
pd3
OUT1
(Current)
OUT15
(Current)
t
pd2
XERR
Figure 15. Grayscale PWM Cycle Timing Chart
SERIAL DATA TRANSFER RATE
Figure 16 shows a cascading connection of n TLC5945 devices connected to a controller, building a basic
module of an LED display system. There is no TLC5945 limitation to the maximum number of ICs that can be
cascaded. The maximum number of cascading TLC5945 devices depends on the application system and is in
the range of 40 devices. Equation 10 calculates the minimum frequency needed:
f
+ 4096 f
(GSCLK)
+ 193 f
(update)
n
f
(SCLK)
(update)
(10)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5945 device
18
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