TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
functional description (continued)
programmable baud rate generator
The TL16C752B UART contains a programmable baud generator that takes any clock input and divides it by
16
a divisor in the range between 1 and (2 –1). An additional divide-by-4 prescaler is also available and can be
selected by MCR[7], as shown in Figure 9. The output frequency of the baud rate generator is 16x the baud rate.
The formula for the divisor is:
divisor = (XTAL1 crystal input frequency/prescaler) / (desired baud rate × 16)
Where:
1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler
4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected)
NOTE:
The default value of prescaler after reset is divide-by-1.
Figure 9 shows the internal prescaler and baud rate generator circuitry.
MCR[7] = 0
Prescaler Logic
(Divide By 1)
Internal
Baud Rate
Clock
for Transmitter
and Receiver
Internal
Oscillator
Logic
Baud Rate
Generator
Logic
XTAL1
XTAL2
Input Clock
Reference
Clock
Prescaler Logic
(Divide By 4)
MCR[7] = 1
Figure 9. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH value are both zero, the UART is effectively
disabled, as no baud clock will be generated.
NOTE:
The programmable baud rate generator is provided to select both the transmit and receive clock
rates.
Table 5 and Table 6 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and
3.072 MHz respectively.
Figure 10 shows the crystal clock circuit reference.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
