TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
functional description (continued)
Table 4. Interrupt Control Functions
PRIORITY
LEVEL
INTERRUPT
TYPE
IIR[5–0]
INTERRUPT SOURCE
INTERRUPT RESET METHOD
000001
000110
None
1
None
None
None
Receiver line
status
OE, FE, PE, or BI errors occur in characters in FE, PE, BI: All erroneous characters are read
the RX FIFO
from the RX FIFO.
OE: Read LSR
001100
000100
2
2
RX timeout
Stale data in RX FIFO
Read RHR
Read RHR
RHR interrupt DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
000010
3
THR interrupt TFE (THR empty)
(FIFO disable)
Read IIR OR a write to the THR
TX FIFO passes above trigger level (FIFO
enable)
000000
010000
100000
4
5
6
Modem status MSR[3:0] = 0
Read MSR
Xoff interrupt
CTS, RTS
Receive Xoff character(s)/special character
Receive Xon character(s)/Read of IIR
RTS pin or CTS pin change state from active Read IIR
(low) to inactive (high)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the
RX FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top
of the FIFO. If the RX FIFO is empty, then LSR[4–2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read
of the LSR.
interrupt mode operation
In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter
by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line stats register (LSR) to see
if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.
IER
IOW/IOR
1
1
1
1
Processor
INT
IIR
THR
RHR
Figure 5. Interrupt Mode Operation
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
