TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Start
Bit
Stop
Bit
Data Bits (5–8)
D3 D4
D0
D1
D2
D5
D6
D7
RX (A–B)
Parity
Bit
Next
Data
Start
Bit
t
d15
Active
Data
Ready
RXRDY (A–B)
RXRDY
t
d16
Active
IOR
Figure 16. Receive Ready Timing in Non-FIFO Mode
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
RX (A–B)
Parity
Bit
First Byte
That Reaches
the Trigger
Level
t
d15
Active
Data
Ready
RXRDY (A–B)
RXRDY
t
d16
Active
IOR
Figure 17. Receive Timing in FIFO Mode
20
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