TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Valid
A0–A2
t
h4
t
su1
Active
CS (A–B)
t
t
h1
d1
t
t
d2
w1
Active
IOR
t
t
d4
d3
Data
D0–D7
Figure 11. General Read Timing
Valid
A0–A2
t
t
su1
h4
Active
CS (A–B)
t
t
h2
d5
t
t
d6
w2
Active
IOW
t
t
h3
su2
Data
D0–D7
Figure 12. General Write Timing
t
d19
IOW
IOR
t
t
h5
su3
XTAL1
Figure 13. Alternate Read/Write Strobe Timing
18
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