TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Active
IOW
t
d7
RTS (A–B)
DTR (A–B)
Change of State
Change of State
CD (A–B)
CTS (A–B)
DSR (A–B)
Change of State
t
t
d8
d8
INT (A–B)
Active
Active
Active
Active
t
d9
Active
t
Active
IOR
d8
RI (A–B)
Change of State
Figure 14. Modem Input/Output Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D3 D4
D0
D1
D2
D5
D6
D7
RX (A–B)
Parity
Bit
Next
Data
Start
Bit
5 Data Bits
6 Data Bits
7 Data Bits
t
d10
INT (A–B)
Active
t
d11
Active
IOR
16 Baud Rate Clock
Figure 15. Receive Timing
19
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TI [ TEXAS INSTRUMENTS ]
