TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 16. Baud Rates Using an 8-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16x CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
10000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
–
0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080
–
0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
52
26
13
9
4
2
1
Table 17. Baud Rates Using a 16-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16x CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
600
1200
1800
2000
20000
13334
9090
7434
6666
3334
1666
834
554
500
416
278
208
138
104
52
0.00
0.00
0.01
0.01
0.01
–0.02
0.04
–0.08
0.28
0.00
0.16
–0.08
0.16
0.64
0.16
0.16
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000000
26
18
8
4
2
1
0.16
–0.79
–2.34
–2.34
–2.34
0.00
34
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