TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
functional block diagram
28
24
CTS0
RTS0
31
25
DSR0
DCD0
RI0
DTR0
29
26
SOUT0
ACE
#1
30
45
9
INT0
41
SIN0
RXRDY0
TXRDY0
32
22
CS0
8
14–21
DB0–DB7
8
13
5
12
11
10
60
61
42
CTS1
DSR1
DCD1
RI1
RTS1
DTR1
8
SOUT1
INT1
ACE
#2
6
62
3
RXRDY1
TXRDY1
SIN1
CS1
35–33
3
A0–A2
IOW
36
37
39
4
Select
and
44
BDO
IOR
Control
Logic
RESET
CLK
8
8
53–46
57
PD0–PD7
INIT
63
ERR
56
65
66
67
68
1
AFD
SLCT
BUSY
PE
55
STB
Parallel
Port
58
SLIN
59
INT2
ACK
PEMD
CS2
38
43
ENIRQ
3
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