TL16C550C, TL16C550CI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177E – MARCH 1994 – REVISED APRIL1998
Terminal Functions (Continued)
TERMINAL
NAME
OUT1
OUT2
NO.
N
34
31
NO.
FN
38
35
NO.
PT
34
31
I/O
O
DESCRIPTION
Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by
setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2
(OUT1) or bit 3 (OUT2) of the MCR.
Receiver clock. RCLK is the 16
×
baud rate clock for the receiver section of the ACE.
Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these
inputs is required for the transfer of data during a read operation; the other input should be tied to its
inactive level (i.e., RD2 tied low or RD1 tied high).
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from
a low to a high level since the last read from the modem status register. If the modem status interrupt
is enabled when this transition occurs, an interrupt is generated.
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive
(high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.
Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When
operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control
register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0
supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in
the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active
but there are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY goes active
(low); when it has been active but there are no more characters in the FIFO or holding register, it goes
inactive (high).
Serial data input. SIN is serial data input from a connected communications device
Serial data output. SOUT is composite serial data output to a connected communication device. SOUT
is set to the marking (high) level as a result of master reset.
Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO
mode, one of two types of DMA signalling can be selected using FCR3. When operating in the
TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are
made continuously until the transmit FIFO has been filled.
5-V supply voltage
Supply common
I
Write inputs. When either WR1 or WR2 is active (low or high respectively) and while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of
these inputs is required to transfer data during a write operation; the other input should be tied to its
inactive level (i.e., WR2 tied low or WR1 tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
RCLK
RD1
RD2
9
21
22
10
24
25
5
19
20
I
I
RI
39
43
41
I
RTS
32
36
32
O
RXRDY
29
32
29
O
SIN
SOUT
TXRDY
10
11
24
11
13
27
7
8
23
I
O
O
VCC
VSS
WR1
WR2
40
20
18
19
44
22
20
21
42
18
16
17
XIN
XOUT
16
17
18
19
14
15
I/O
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DALLAS, TEXAS 75265
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TI [ TEXAS INSTRUMENTS ]
