TL16C550C, TL16C550CI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177E – MARCH 1994 – REVISED APRIL1998
functional block diagram
S
e
l
e
c
t
Internal
Data Bus
8
8
Receiver
FIFO
8 –1
D(7 – 0)
Data
Bus
Buffer
Receiver
Buffer
Register
Receiver
Shift
Register
10
SIN
Line
Control
Register
A0
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
28
27
26
12
13
14
25
35
21
22
18
19
23
24
16
Modem
Control
Register
Modem
Status
Register
8
Select
and
Control
Logic
Transmitter
Holding
Register
Line
Status
Register
Transmitter
FIFO
8
S
e
l
e
c
t
Divisor
Latch (LS)
Divisor
Latch (MS)
Receiver
Timing and
Control
9
RCLK
32
RTS
Baud
Generator
15
BAUDOUT
Transmitter
Timing and
Control
Autoflow
Control
(AFE)
8
Transmitter
Shift
Register
11
SOUT
36
33
8
Modem
Control
Logic
37
38
39
34
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
XOUT 17
29
RXRDY
VCC
VSS
40
20
Power
Supply
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
8
Interrupt
Control
Logic
31
30 INTRPT
8
NOTE A: Terminal numbers shown are for the N package.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
TI [ TEXAS INSTRUMENTS ]
