THS4531
SLOS358B –SEPTEMBER 2011–REVISED MARCH 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
CHANNEL
COUNT
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
1
1
1
1
1
1
T4531
T4531
4531
4531
4531
4531
THS4531ID
THS4531IDR
Rails, 75
SOIC-8
VSSOP-8
WQFN-10
D
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Tape and reel, 2500
Rails, 80
THS4531IDGK
THS4531IDGKR
THS4531IRUNT
THS4531IRUNR
THS4531
DGK
RUN
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
VALUE
UNITS
Supply voltage, VS– to VS+
5.5
Input/output voltage, VIN±, VOUT±, and VOCM pins
Differential input voltage, VID
(VS–) – 0.7 to (VS+) + 0.7
V
V
1
Continuous output current, IO
50
mA
mA
Continuous input current, Ii
0.75
Continuous power dissipation
See Thermal Information
Maximum junction temperature, TJ
Operating free-air temperature range, TA
Storage temperature range, Tstg
150
–40 to +125
–65 to +150
3000
°C
°C
°C
V
Human body model (HBM)
Electrostatic
discharge (ESD) Charge device model (CDM)
500
V
ratings:
Machine model (MM)
200
V
THERMAL INFORMATION
THS4531
THS4531
THS4531
VSSOP
(MSOP)
(DGK)
SOIC
(P)
WQFN
(RUN)
THERMAL METRIC(1)
UNITS
8 PINS
133
78
8 PINS
198
84
10 PINS
163
66
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
73
120
19
113
17
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26
ψJB
73
118
N/A
113
N/A
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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