TCA6424A
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SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Data From Lower
or Upper Byte
of Register
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Master
Slave Address
Slave Address
AD
DR
AD
DR
Command Byte
S
0
1
0
0
0
1
0
A
A
S
0
1
0
0
0
1
1
A
MSB
Data
LSB A
First Byte
R/W
R/W
At this moment, master transmitter
becomes master receiver, and
slave receiver becomes slave transmitter.
Data From Upper
or Lower Byte
of Register
No Acknowledge
From Master
MSB
LSB NA P
Data
Last Byte
Figure 8. Read From Register
<br/>
1
2
3
4
5
6
7
8
9
SCL
SDA
I0.x
Data 1
I1.x
I2.x
I0.x
AD
DR
S
0
1
0
0
0
1
1
A
A
Data 2
A
Data 3
A
Data 4
1 P
R/W
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
Read From
Port 0
Data Into
Port 0
Read From
Port 1
Data Into
Port 1
INT
t
t
iv
ir
Read From
Port 2
Data Into
Port 2
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
C. Auto-increment mode is enabled.
Figure 9. Read Input Port Register
Copyright © 2010, Texas Instruments Incorporated
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