SLOS559 – JUNE 2008
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
BST_C
BST_D
CONFIG_2
CONFIG_1
DVDD
DVSS
DVSSO
FAULT
FORMAT2
FORMAT1
FORMAT0
GAIN_1
GAIN_0
GND
GVDD_AB
GVDD_CD
LRCLK
MCLK
MUTE
NO.
56
45
33
34
15, 35
26
20
9
30
31
32
28
29
41, 42
5
44
22
36
21
I/O
(1)
P
P
P
P
P
P
P
DO
DI
DI
DI
DI
DI
P
P
P
DI
DI
DI
5-V
5-V
5-V
Pullup
5-V
5-V
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
5-V
TOLERANT
TERMINATION
(2) (3)
DESCRIPTION
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
Input/output configuration. Connect this terminal directly to GND.
Input/output configuration. Connect this terminal directly to DVDD.
3.3-V Digital power supply
Digital ground
Oscillator ground
Overtemperature, undervoltage, and overcurrent fault reporting.
Active low indicates fault. If high, normal operation.
Digital data format select MSB.
Digital data format select LSB.
Digital data format select.
MSB of gain select.
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
Analog ground for power stage.
Gate drive voltage for half-bridges A and B (10.8 V to 13.2 V)
Gate drive voltage for half-bridges C and D (10.8 V to 13.2 V)
Input serial audio data left/right clock (sampling rate clock)
Clock master input. The input frequency of this clock can range from
4.9 MHz to 49 MHz.
Performs a soft mute of outputs, active-low. A logic low on this pin
sets the outputs equal to 50% duty cycle. A logic high on this pin
allows normal operation. The mute control provides a noiseless
volume ramp to silence. Releasing mute provides a noiseless ramp to
previous volume.
Analog overcurrent programming. Requires 22-kΩ resistor to ground.
Oscillator trim resistor. Connect an 18.2-kΩ (1% tolerance is
required) resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
OC_ADJ
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
8
19
1, 64
60, 61
52, 53
48, 49
17
AO
AO
O
O
O
O
DI
5-V
Pullup
Power down, active-low. PDN stops all clocks, and outputs stop
switching whenever a logic low is applied. When PDN is released, the
device powers up all logic, starts all clocks, and performs a soft start
that returns to the previous configuration changes to FORMATx and
GAINx pins are ignored on PDN cycling.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A (0 V–21 V)
Power supply input for half-bridge output B (0 V–21 V)
Power supply input for half-bridge output C (0 V–21 V)
Power supply input for half-bridge output D(0 V–21 V)
PGND_AB
PGND_CD
PLL_FLTM
PLL_FLTP
PVDD_A
PVDD_B
PVDD_C
PVDD_D
62, 63
50, 51
12
13
2, 3
58, 59
54, 55
46, 47
P
P
AO
AI
P
P
P
P
6
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