SLOS559 – JUNE 2008
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DISSIPATION RATINGS
PACKAGE
(1)
T
A
≤
25°C
POWER RATING
5W
DERATING FACTOR
ABOVE T
A
= 25°C
40 mW/°C
(2)
T
A
= 45°C
POWER RATING
3.2 W
T
A
= 70°C
POWER RATING
2.6 W
10 × 10 QFP
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs
for more information about using the
HTQFP thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Gate drive supply voltage
Output bridge supply voltage
Digita supply voltage
Analog supply voltage
V
IH
V
IL
T
A
T
J
R
L
(BTL)
R
L
(SE)
R
L
(PBTL)
L
O
(BTL)
L
O
(SE)
L
O
(PBTL)
Output-filter inductance
Minimum output inductance under
short-circuit condition
Load impedance
Output filter: L = 22
µH,
C = 680 nF.
High-level input voltage
Low-level input voltage
Operating ambient temperature range
Operating junction temperature range
GVDD, VDD
PVDD
DVDD
AVDD
3.3-V TTL, 5-V tolerant
3.3-V TTL, 5-V tolerant
0
0
6.0
3.2
3.2
8
4
4
10
10
10
µH
Ω
10.8
0
3
3
2
0.8
85
150
3.3
3.3
NOM
12
MAX
13.2
21
3.6
3.6
UNIT
V
V
V
V
V
V
°C
°C
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate 2×–1×
oversampled
TEST CONDITIONS
32–kHz data rate ±2%
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±2%
MODE
12× sample rate
8×, 4×, and 2× sample rates
8×, 4×, and 2× sample rates
VALUE
384
352.8
384
UNIT
kHz
kHz
kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
f
MCLKI
Frequency, MCLK (1 / t
cyc2
)
MCLK duty cycle
MCLK minimum high time
MCLK minimum low time
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
External PLL filter capacitor C2
External PLL filter resistor R
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
47
4.7
470
≥2-V
MCLK = 49.152 MHz, within the
min and max duty cycle constraints
≤0.8-V
MCLK = 49.152 MHz, within the
min and max duty cycle constraints
TEST CONDITIONS
MIN
4.9
40%
8
8
4
50%
TYP
MAX
49.2
60%
ns
ns
MCLKs
nF
nF
Ω
UNIT
MHz
8
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