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SLOS559 – JUNE 2008
64-PIN, HTQFP PACKAGE (TOP VIEW)
PAP Package
(Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD_AB
VDD
TEST1
OC_ADJ
FAULT
AVDD
AVSS
PLL_FLTM
PLL_FLTP
VR_ANA
DVDD
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
VREG
GND
GND
SUB_PWM+
SUB_PWM–
VALID
BKND_ERR
MCLK
DVDD
CONFIG_1
CONFIG_2
MUTE
LRCLK
SCLK
SDIN2
SDIN1
DVSS
VR_DIG
PDN
VREG_EN
OSC_RES
GAIN_1
GAIN_0
FORMAT2
FORMAT1
FORMAT0
DVSSO
PGND_AB
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
PGND_CD
PGND_CD
OUT_D
PGND_AB
OUT_A
P0071-03
TERMINAL FUNCTIONS
TERMINAL
NAME
AVDD
AVSS
BKND_ERR
NO.
10
11
37
I/O
(1)
P
P
DI
Pullup
5-V
TOLERANT
TERMINATION
(2) (3)
DESCRIPTION
3.3-V Analog power supply
Analog 3.3-V supply ground
Active low. A back-end error sequence is initiated by applying a logic
low to this pin. Connect to an external power stage. If no external
power stage is used, connect directly to DVDD.
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
BST_A
BST_B
4
57
P
P
(1)
(2)
(3)
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are 20-µA
weak
pullups and all pulldowns are 20-µA
weak
pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups
→
logic 1 input; pulldowns
→
logic 0 input). Devices that drive
inputs with pullups must be able to sink 50
µA
while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 50
µA
while maintaining a logic-1 drive level.
If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
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