SLOS559 – JUNE 2008
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FAULT
Under-
voltage
Protection
4
4
VREG
Power
On
Reset
Internal Pullup
Resistors to VREG
FAULT
Protection
and
I/O Logic
AGND
Temp.
Sense
VALID
Overcurrent
Protection
I
sense
GND
OC_ADJ
BST_D
PVDD_D
PWM_D
PWM
Rcv
Ctrl
Timing
Gate
Drive
BTL-Configuration
Pulldown Resistor
OUT_D
PWM Controller
GVDD_CD
Regulator
PGND_CD
GVDD_CD
BST_C
PVDD_C
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
BTL-Configuration
Pulldown Resistor
OUT_C
PGND_CD
BST_B
PVDD_B
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
BTL-Configuration
Pulldown Resistor
OUT_B
GVDD_AB
Regulator
PGND_AB
GVDD_AB
BST_A
PVDD_A
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
BTL-Configuration
Pulldown Resistor
OUT_A
PGND_AB
B0034-04
Figure 1. Power Stage Functional Block Diagram
4
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