TAS5715
SLOS645 –AUGUST 2010
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Headphone Configuration
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Registers 0x07–0x0B
Register 0x19
Master/channel headphone volume
SDG = 0x30 or 0x00 (PWM3/4 in SDG)
ICD1/2 = {0xAC, 0x54}
Registers 0x11–0x12
Register 0x1A<7>
Register 0x1A<4:0>
Register 0x20<23>
Register 0x20<19>
Register 0x46<1:0>
Register 0x50<7>
Clear bit for headphone mode (HP/SPKR = 0)
Set to 0 0000 for 0-ms start/stop period
Clear bit for Ch1 AD mode
Clear bit for Ch2 AD mode
Clear both bits to disable DRC1 and DRC2
Set bit to disable EQ
Headphone Mode Power Down
HP/SPKR
(SE/BTL)
VALID
PWM_A(L+)
PWM_C(R+)
HPL/R
HPL/R
t(exitSDHP)
t(HPamp)
t(exitSDHPamp)
PWM_B(L–)
PWM_D(R–)
FAULT = 1 Output
HPSD
(A0/FAULT)
Hi-Z (Ext. Pulldown)
I2C: SCL
SDA
Enable
FAULT
t(PDN-HPSD)
PDN
T0453-01
PARAMETE
R
DESCRIPTION
MIN
TYP MAX
UNIT
ms
t(PDN-HPSD)
Delay from power-down event to headphone amplifier shutdown assertion
2
Exit shutdown wait time before enabling external headphone amp (t(HPchg)
given by register 0x1A<6:5>)
t(exitSDHP)
1 + 1.3 × t(HPchg)
ms
Headphone amp exit shutdown wait time before unmuting (t(HPamp) given by
register 0x1C<7:4>)
1 + 1.3 ×
t(HPamp)
t(exitSDHPamp)
t(HPamp)
ms
ms
Headphone amp enable/disable wait time (given by register 0x1C<7:4>)
t(HPamp)
Figure 58. Headphone Control Power Down
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